The UltraSparc T1Posted: January 20, 2006
Jim Dinan gave a presentation at last night’s Open Source Club meeting on the UltraSPARC T1 processor. With 32 simultaneous threads (8 cores, 4 threads/core), this CMT monster sports a 134GB/sec crossbar and four on-chip MMUs for a total memory bandwidth of 25.6GB/sec. Also impressive: it does all of this with a peak power consumption of 79 watts. (For comparison, a dual-core Xeon (Paxville) consumes around 165 watts.)
Don’t go rushing out to buy one just yet, though; this isn’t a processor for your Average Joe – at least not if Joe wants to do any floating point computations. The T1 has a single, shared FPU hanging off of the bus. “How many?!”, you ask incredulously. That’s right…one. This chip is meant for data centers (read: high-volume web service/OLTP servers), not for any kind of scientific computing. Another prohibitive factor: price. Keep in mind, this is a Sun “price is no object…until we go out of business because we don’t sell anything” MicroSystems chip we’re talking about; looks like a fairly “standard” server with the T1 is going to run upwards of fourteen grand.
“So…why is this of interest to an open source club?” Well, that’s probably the coolest thing of all. Sun has begun the OpenSPARC Initiative – the first of its stated goals is, “To significantly increase participation in processor architecture development and application design by making cutting-edge hardware IP freely available” – and the UltraSPARC T1 is going to be the first processor to have its Verilog source released under this initiative.
Update: Anandtech has some more technical details and benchmarks for the T1 (if you can look past the heinous advertising).